Signals between a hardware IP and the parent system design are incorrectly connected causing security risks.
Individual hardware IP must communicate with the parent system in order for the product to function correctly and as intended. If implemented incorrectly, while not causing any apparent functional issues, may cause security issues. For example, if the IP should only be reset by a system-wide hard reset, but instead the reset input is connected to a software-triggered debug mode reset (which is also asserted during a hard reset), integrity of data inside the IP can be violated.
Threat Mapped score: 0.0
Industry: Finiancial
Threat priority: Unclassified
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| Phase | Note |
|---|---|
| Implementation | This weakness is introduced when integrating IP into a parent design. |
Intro: Many SoCs use hardware to partition system resources between trusted and un-trusted entities. One example of this concept is the Arm TrustZone, in which the processor and all security-aware IP attempt to isolate resources based on the status of a privilege bit. This privilege bit is part of the input interface in all TrustZone-aware IP. If this privilege bit is accidentally grounded or left unconnected when the IP is instantiated, privilege escalation of all input data may occur.
Body: In the Verilog code below, the security level input to the TrustZone aware peripheral is correctly driven by an appropriate signal instead of being grounded.
// IP definition module tz_peripheral(clk, reset, data_in, data_in_security_level, ...); input clk, reset; input [31:0] data_in; input data_in_security_level; ... endmodule // Instantiation of IP in a parent system module soc(...) ... tz_peripheral u_tz_peripheral( .clk(clk), .rst(rst), .data_in(rdata), //Copy-and-paste error or typo grounds data_in_security_level (in this example 0=secure, 1=non-secure) effectively promoting all data to "secure") .data_in_security_level(1'b0), ); ... endmoduleIntro: Here is a code snippet from the Ariane core module in the HACK@DAC'21 Openpiton SoC [REF-1362]. To ensure full functional correctness, developers connect the ports with names. However, in some cases developers forget to connect some of these ports to the desired signals in the parent module. These mistakes by developers can lead to incorrect functional behavior or, in some cases, introduce security vulnerabilities.
Body: In the above example from HACK@DAC'21, since interrupt signals are not properly connected, the CSR module will fail to send notifications in the event of interrupts. Consequently, critical information in CSR registers that should be flushed or modified in response to an interrupt won't be updated. These vulnerabilities can potentially result in information leakage across various privilege levels.
... csr_regfile #( ... ) csr_regfile_i ( .flush_o ( flush_csr_ctrl ), .halt_csr_o ( halt_csr_ctrl ), ... .irq_i(), .time_irq_i(), .* ); ...