CWE-1255: Comparison Logic is Vulnerable to Power Side-Channel Attacks

Description

A device's real time power consumption may be monitored during security token evaluation and the information gleaned may be used to determine the value of the reference token.

Extended Description

The power consumed by a device may be instrumented and monitored in real time. If the algorithm for evaluating security tokens is not sufficiently robust, the power consumption may vary by token entry comparison against the reference value. Further, if retries are unlimited, the power difference between a "good" entry and a "bad" entry may be observed and used to determine whether each entry itself is correct thereby allowing unauthorized parties to calculate the reference value.

ThreatScore

Threat Mapped score: 0.0

Industry: Finiancial

Threat priority: Unclassified

Observed Examples (CVEs)

CVE: CVE-2020-12788

CMAC verification vulnerable to timing and power attacks.

Related Attack Patterns (CAPEC)

CAPEC-189

Attack TTPs

N/A

Modes of Introduction

Phase	Note
Architecture and Design	The design of the algorithm itself may intrinsically allow the power side channel attack to be effective
Implementation	This weakness may be introduced during implementation despite a robust design that otherwise prevents exploitation

Common Consequences

Impact: Modify Memory, Read Memory, Read Files or Directories, Modify Files or Directories, Execute Unauthorized Code or Commands, Gain Privileges or Assume Identity, Bypass Protection Mechanism, Read Application Data, Modify Application Data, Hide Activities — Notes: As compromising a security token may result in complete system control, the impacts are relatively universal.

Potential Mitigations

Architecture and Design: The design phase must consider each check of a security token against a standard and the amount of power consumed during the check of a good token versus a bad token. The alternative is an all at once check where a retry counter is incremented PRIOR to the check. (N/A)
Architecture and Design: Another potential mitigation is to parallelize shifting of secret data (see example 2 below). Note that the wider the bus the more effective the result. (N/A)
Architecture and Design: An additional potential mitigation is to add random data to each crypto operation then subtract it out afterwards. This is highly effective but costly in performance, area, and power consumption. It also requires a random number generator. (N/A)
Implementation: If the architecture is unable to prevent the attack, using filtering components may reduce the ability to implement an attack, however, consideration must be given to the physical removal of the filter elements. (N/A)
Integration: During integration, avoid use of a single secret for an extended period (e.g. frequent key updates). This limits the amount of data compromised but at the cost of complexity of use. (N/A)

Applicable Platforms

None (Not Language-Specific, Undetermined)

Demonstrative Examples

Intro: Consider an example hardware module that checks a user-provided password (or PIN) to grant access to a user. The user-provided password is compared against a stored value byte-by-byte.

Body: Since the algorithm uses a different number of 1's and 0's for password validation, a different amount of power is consumed for the good byte versus the bad byte comparison. Using this information, an attacker may be able to guess the correct password for that byte-by-byte iteration with several repeated attempts by stopping the password evaluation before it completes.

static nonvolatile password_tries = NUM_RETRIES; do while (password_tries == 0) ; // Hang here if no more password tries password_ok = 0; for (i = 0; i < NUM_PW_DIGITS; i++) if (GetPasswordByte() == stored_password([i]) password_ok |= 1; // Power consumption is different here else password_ok |= 0; // than from here end if (password_ok > 0) password_tries = NUM_RETRIES; break_to_Ok_to_proceed password_tries--; while (true) // Password OK

Intro: This code demonstrates the transfer of a secret key using Serial-In/Serial-Out shift. It's easy to extract the secret using simple power analysis as each shift gives data on a single bit of the key.

Body: This code demonstrates the transfer of a secret key using a Parallel-In/Parallel-Out shift. In a parallel shift, data confounded by multiple bits of the key, not just one.

module siso(clk,rst,a,q); input a; input clk,rst; output q; reg q; always@(posedge clk,posedge rst) begin if(rst==1'b1) q<1'b0; else q<a; end endmodule

Notes

No notes available.

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